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Introduction to Chip Testability Design Technology (DFT)

2024-09-20 17:29
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Testing vs. Verification

Cost of Testing

• Design for testability (DFT)                                                                                             
• Hardware design styles or added hardware that reduces test generation complexity                         
• Chip area and performance overhead  
• Software processes of test
• Test generation and fault simulation
• Test programming and debugging
• Manufacturing test
• Automatic test equipment (ATE) capital cost
  • ~$5M initial cost + ~$2M per year
• Test center operational cost
   • ~5 cent/second (~$1.5M/year for 24hour operation)
Introduction to Chip Testability Design Technology (DFT)-Cost of Testing                                                  

Cost of NOT Testing

• Cost of defective ICs
• IC
• IC on a PCB (printed circuit board)
• IC on a PCB in a system
• IC on a PCB in a system in field
• The most expensive defect is the one that wasn’t detected inline
• Detect defective parts as soon as possible!
Introduction to Chip Testability Design Technology (DFT)-Cost of NOT Testing
 

Production Testing

Introduction to Chip Testability Design Technology (DFT)-Production Testing
• Testing after chip fabrication in order to detect manufacturing defects that may impact functionality or electrical parameters.
• Manufacturing test ideally would check every node in the circuit to prove it is operational.
Introduction to Chip Testability Design Technology (DFT)-Production Testing

Production Test Flow

Introduction to Chip Testability Design Technology (DFT)-Production Test Flow
• Wafer-level testing (Wafer Sort)
• Assembly & Packaging
• Open/Short test
• Packaged device test
• Burn-In (@ elevated voltage and temperature)
• Final Test (pass/fail) and Bin Sorting
• Parametric Tests (voltage, temperature, and clock)
• Shmoo plot
Introduction to Chip Testability Design Technology (DFT)-Production Test Flow
 

Wafer Sort

• Wafer sort or probe test
• Done before wafer is scribed and cut into chips
• Includes test site characterization – specific test devices are checked with specific patterns to measure gate threshold, poly sheet resistance, etc.
• Probe card
• Custom built PCB to allow performing wafer sort
• Modern probe cards can test an entire 12" wafer with one touchdown
• Can contact several dies in parallel (~1-16)
• Camera in the wafer prober allows alignment
Introduction to Chip Testability Design Technology (DFT)-Wafer Sort
 

Electrical Testing

• DC Parametric Tests
• DC contact test - Calculates pin resistance
• Power consumption test - Measure max current at worst case temperature
• Output short circuit test - Measure current driven when output short circuited
• Output drive current test - Measure current for ‘1’ and ‘0’ outputs
• Threshold test - Measure VIH, VIL of input pads
• AC Parametric Tests
• Rise/Fall time tests
• Setup/Hold time tests
• Propagation delay tests
 

Burn-in or Stress Test

• Process:
• Subject chips to high temperatures and over-voltage supply, while running production tests 
• For example: 125C for 168 hours
• Catches:
• Infant mortality cases – these are damaged or weak (low reliability) chips that will fail in the first few days of operation – burn-in causes bad devices to fail before they are shipped to customers
• Freak failures – devices having the same failure mechanisms as reliable devices
Introduction to Chip Testability Design Technology (DFT)-Burn-in or Stress Test
 
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Next: What is the 1n4148 diode used for?

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